1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, in particular, a semiconductor integrated circuit having a protective circuit for protecting an output transistor against overvoltage.
2. Description of Related Art
For automobiles and home electrical products, a power IC (integrated circuit, also called “power semiconductor”) having a switching element for controlling a voltage or current has been used. In response thereto, various techniques for protecting this switching element from overvoltage have been proposed (see Japanese Unexamined Patent Publication No. 2002-151989, for example). To give an example of the overvoltage, there are a counter electromotive force applied from the inductive load side and a dump surge applied from the power supply side.
FIG. 10 is a circuit diagram showing the configuration of a conventional power IC 91. The conventional power IC 91 includes an output MOS transistor M0 that is a metal oxide semiconductor field effect transistor (MOSFET, hereinafter also referred to as “MOS” or “MOS transistor”) as a switching element for controlling current. In the illustrated example, the output MOS transistor M0 is connected with the power supply ahead of a load (inductive load 3), and so functions as a high-side switch. The inductive load 3 is, for example, an actuator, which is an equivalent circuit composed of an inductance component and a resistance component.
In this embodiment, the terms “off”, “on”, “turn-off”, and “turn-on” mean, if used singly, “off”, “on”, “turn-off”, and “turn-on” of the output MOS transistor, respectively. The transition of the MOS transistor from an on state to a completely off state is called “turn-off”, and the transition of the MOS transistor from an off state to a completely on state is called “turn-on”.
The output MOS transistor M0 has a drain supplied with power through a terminal Vbb (power supply terminal), has a gate whose voltage is boosted by a charge pump circuit 12 through a resistor R3, and has a source connected with the inductive load 3 through an terminal OUT (output terminal). A gate discharge MOS transistor N1 for discharging the gate of the output MOS transistor M0 has a drain connected with a node between the charge pump circuit 12 and the resistor R3, has a gate receiving a control signal S2, and has a source connected with the terminal OUT.
The charge pump circuit 12 is turned on/off in response to a control signal S1 supplied from a microprocessor or the like, and the gate discharge MOS transistor N1 is turned on/off in response to the control signal S2 supplied from the microprocessor or the like.
Further, the conventional power IC 91 includes a dynamic clamp circuit 31 for protecting the output MOS transistor M0 from breakdown due to the counter electromotive force, which is provided between the drain and gate of the output MOS transistor M0. The dynamic clamp circuit 31 includes a high-voltage diode D6 and a backflow preventive diode D7.
The counter electromotive force Vinv at the turn-off results from the emission of energy ((½)·L·IOUT·IOUT) accumulated in the inductance component of the inductive load 3. During the turn-off, according as a gate-source voltage Vgs of the output MOS transistor drops, an output voltage VOUT decreases to generate the counter electromotive force Vinv. At this time, if the output voltage VOUT falls down to the breakdown voltage of the high-voltage diode D6, the counter electromotive force Vinv is clamped to prevent the voltage application to the output MOS transistor M0 from going beyond the withstand voltage thereof.
On the other hand, in the conventional power IC 91, if a battery as the power supply is connected with an alternator, and a battery terminal connected with the battery falls off during the power generation of the alternator, positive overvoltage called “dump surge” (about 60 V) is applied to the terminal Vbb.
When the dump surge is applied under the off-state of the output MOS transistor M0, and clamping function of the dynamic clamp circuit 31 is activated, the output MOS transistor M0 is broken due to overheat of its own. Thus, it is necessary to set the breakdown voltage of the high-voltage diode D6 to a value not less than 60 V of the dump surge. Further, the withstand voltage of the output MOS transistor M0 should be set to a value not less than the breakdown voltage of the high-voltage diode D6. In order to keep the same on-resistance of the output MOS transistor M0, a chip area has to be enlarged in proportion to the withstand voltage of the output MOS transistor M0. A power IC having the dynamic clamp circuit 31 needs a larger chip area than a power IC without the dynamic clamp circuit 31. As a result, A power IC having the dynamic clamp circuit 31 is more expensive.
In view of such problems, the applicants of the present invention propose a semiconductor integrated circuit where a clamp controlling circuit for controlling a clamp circuit operation is provided to minimize a chip area in Japanese Unexamined Patent Publication No. 2005-223399 (corresponding U.S. patent application Ser. No. 11/035,060).
FIG. 11 is a circuit diagram showing the configuration of a conventional power IC 92 as disclosed in Japanese Unexamined Patent Publication No. 2005-223399. This conventional power IC includes a clamp controlling circuit 32 in addition to the configuration of FIG. 10. The clamp controlling circuit 32 includes a MOS transistor N2, a clamp switch MOS transistor P5, and a resistor R4.
The MOS transistor N2 has a drain connected with a terminal Vbb through the resistor R4, has a gate connected with a gate of an output MOS transistor M0, and has a source connected with a terminal OUT. The clamp switch MOS transistor P5 has a source connected with the terminal Vbb, has a gate connected with a node between the resistor R4 and the drain of the MOS transistor N2, and has a drain connected with the dynamic clamp circuit 31.
FIG. 12 is a waveform diagram of each signal when the output MOS transistor M0 is switched from on to off and then from off to on, in the conventional power IC 92.
To switch the output MOS transistor M0 from on to off, the control signal S1 is set LOW (low level) to stop the application of boosted voltage from the charge pump circuit 12. Further, the control signal S2 is set HIGH (high level) to turn on the gate discharge MOS transistor N1 and let gate charges of the output MOS transistor M0 flow into the terminal OUT through the resistor R3 and the gate discharge MOS transistor N1. As a result, the gate-source voltage Vgs decreases to turn off the output MOS transistor M0. Accordingly, the output current IOUT stops flowing and the output voltage VOUT comes to zero.
During a turn-off period of the output MOS transistor M0, the MOS transistor N2 is turned on due to the potential of the gate-source voltage Vgs. A voltage VR across the resistor R4 increases to turn on the clamp switch MOS transistor P5 and let the dynamic clamp circuit 31 operate. Then, the counter electromotive force Vinv that is generated with the inductive load 3 at this time is clamped with the dynamic clamp circuit 31. In this way, the conventional power IC 92 activates the dynamic clamp circuit 31 during the turn-off period.
According to the power IC 92, the withstand voltage of the output MOS transistor M0 can be therefore set without considering the breakdown voltage of the high-voltage diode D6, making it possible to reduce the withstand voltage of the output MOS transistor M0 and minimize the chip area.
However, the conventional power IC 92 of FIG. 11 has a problem that if the chip area is minimized as above, when the dump surge occurs under the off-state of the output MOS transistor M0, the output MOS transistor M0 would break.
This problem is caused due to the fact that when the dump surge occurs to abruptly increase the drain-source voltage of the output MOS transistor M0, a drain-gate or drain-source parasitic capacitance of the output MOS transistor M0 generates the voltage between the gate and source of the output MOS transistor M0.
FIG. 13 shows an equivalent circuit under the off state of the output MOS transistor in the conventional power IC 92 of FIG. 11, from which the clamp controlling circuit 32 is removed. Denoted by RN1 is an on resistance of the gate discharge MOS transistor N1. Denoted by Cdg and Cgd are a drain-gate capacitance (parasitic capacitance) and a gate-source capacitance (parasitic capacitance) of the output MOS transistor MO.
For ease of explanation, an equivalent circuit where an impedance of the inductive load 3 is set to 0 is shown in FIG. 14. Referring to the equivalent circuit of FIG. 14, a transient response (step response) of the gate-source voltage Vgs upon the occurrence of the dump surge is represented by following expressions.
                              Cdg          ⁢                                                    ⅆ                V                            ⁢                              ⅆ                g                                                    ⅆ              t                                      =                              Cgs            ⁢                                          ⅆ                Vgs                                            ⅆ                t                                              +                      Vgs            R                                              (                  Expression          ⁢                                          ⁢          1                )                                Vbb        =                              Vdg            +            Vgs                    =                      {                                                                                                      V                      0                                        ⁡                                          (                                              t                        <                        0                                            )                                                                                                                                                              V                      1                                        ⁡                                          (                                              t                        >                        0                                            )                                                                                                                              (                  Expression          ⁢                                          ⁢          2                )                                          Cdg          ×          s          ×                      Vdg            ⁡                          (              s              )                                      =                              Cgs            ×            s            ×                          Vgs              ⁡                              (                s                )                                              +                                    1              R                        ⁢                          Vgs              ⁡                              (                s                )                                                                        (                  Expression          ⁢                                          ⁢          3                )                                                      Vdg            ⁡                          (              s              )                                +                      Vgs            ⁡                          (              s              )                                      =                              V            1                    -                      V            0                                              (                  Expression          ⁢                                          ⁢          4                )                                          Vgs          ⁡                      (            s            )                          =                              (                                          V                1                            -                              V                0                                      )                    ⁢                      Cdg                          Cdg              +              Cgs                                ×                      1                          s              +                              1                                                      (                                          Cdg                      +                      Cgs                                        )                                    ⁢                  R                                                                                        (                  Expression          ⁢                                          ⁢          5                )                                          Vgs          ⁡                      (            t            )                          =                              (                                          V                1                            -                              V                0                                      )                    ⁢                      Cdg                          Cdg              +              Cgs                                ×                      exp            ⁡                          (                                                -                                      1                                                                  (                                                  Cdg                          +                          Cgs                                                )                                            ⁢                      R                                                                      ⁢                t                            )                                                          (                  Expression          ⁢                                          ⁢          6                )            
That is, an amount of current flowing through the parasitic capacitance Cdg is the sum of current flowing through the resistor R3 and current flowing through the parasitic capacitance Cgs, so Expression 1 is established. In Expression 1, Vdg represents a drain-gate voltage of the output MOS transistor MO, and R represents the sum of resistance of the resistor R3 and the on resistance RN1 of the gate discharge MOS transistor N1. Expression 2 represents the dump surge based on a unit step input. In Expression 2, Vbb represents a voltage at the terminal Vbb, V0 represents a general voltage, V1 represents a dump surge voltage, and t represents the time. The Laplace transform of Expressions 1 and 2 gives Expressions 3 and 4, respectively.
Further, omitting the drain-gate voltage Vdg (s) from Expressions 3 and 4 gives Expression 5. The inverse Laplace transform of Expression 5 gives Expression 6, which represents the transient response of the gate-source voltage Vgs.
As apparent from Expression 6, just after the occurrence of the dump surge (t=0), Vgs=(V1−V0)·Cdg/(Cdg+Cgs). If the gate-source voltage Vgs reaches or exceeds a threshold Vt2 of the MOS transistor N2 in the clamp controlling circuit 32, the MOS transistor N2 is turned on, and the clamp controlling circuit 32 makes the dynamic clamp circuit 31 operate.
For example, provided that Cdg=Cgs/10, V1=60V, and V0=12V, Vgs=4.4 V. The threshold of the output MOS transistor MO is defined as Vt0. Unless Vt2<Vt0, the clamping is impossible during the turn-off period, so Vt2 should be lower than Vt0. In general, Vt0 is about 1 to 3 V. Therefore, just after the dump surge, the gate-source voltage Vgs reaches or exceeds the threshold Vt2 of the MOS transistor N2 in the clamp controlling circuit 32. Therefore, in the conventional power IC 92, the dynamic clamp circuit 31 operates like the conventional power IC 91 of FIG. 10 if activated upon the dump surge.
FIG. 15 is a timing chart showing that the dump surge takes place in the conventional power IC 92 and the dynamic clamp circuit 31 operate. The potential at the terminal Vbb is, for example, 12V of the power supply voltage but would reach about 60V upon the dump surge and remain at the voltage level for 0.2 to 0.4 seconds. At this time, the gate-source voltage Vgs also increases, and if the voltage reaches or exceeds the threshold Vt2, the dynamic clamp circuit 31 starts operating. In addition, if the voltage at the terminal Vbb exceeds the breakdown voltage of the high-voltage diode D6, the clamping function is exerted to temporarily turn on the output MOS transistor M0. As a result, the output current IOUT starts flowing. Accordingly, in the conventional power IC 92, if the withstand voltage of the output MOS transistor M0 is set without considering the breakdown voltage of the high-voltage diode D6, the output MOS transistor MO breaks.